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Circuit Semantics Meets 2003 Milestones, Unveils 2004 Plans
Products Will Improve Performance and Simulator Support, Add
Signal Integrity, Power Characterization, Noise and Functional
Modeling Capabilities
MOUNTAIN VIEW, Calif.—(BUSINESS WIRE)—Jan. 15, 2004—
Circuit Semantics, Inc. (CSI), the leading provider of timing and
characterization solutions for high-performance circuit design, today
announced that it has achieved several significant milestones in the
past year, and put together its 2004 product plan. Last year, the
company licensed its patents for $9 million, closed a $1.6 million
funding round with previous investors VenGlobal and Crescent Ventures
leading the round and moved its headquarters to Mountain View,
California.
"The round of VC funding, licensing income, and growing interest
from current and new customers are the elements that are allowing us
to expand our staff and add new capabilities to our products this
year," remarked Ewald Detjens, president and CEO of Circuit Semantics.
In 2004, Circuit Semantics plans to add R&D engineers, marketing,
sales and application staff, as well as features to its
characterization and modeling tools. Sanjay Rohatgi, vice president of
applications at Circuit Semantics, also noted, "We plan to add several
significant product capabilities this year."
2004 Product Plans
DynaCore(TM), in addition to its timing sign-off capabilities,
will add signal integrity, power characterization and functional
modeling. Thus, a single run of DynaCore will be able to characterize
and analyze the design in various inter-dependent domains. This
concurrent characterization and analysis is warranted by nanometer
technology for successful silicon.
Support for industry standard simulators will also be
significantly enhanced, so customers using DynaCell(TM) with these
simulators could experience up to a 7 to 10x performance improvement.
In addition to DynaCell shipping now with noise characterization,
plans are in place to add support for Synopsys' SPDM format and the
IEEE 1603 Advanced Library Format (ALF).
More About Circuit Semantics Products
Circuit Semantics offers DynaCell for characterization of cell
libraries, DynaCore for timing sign-off and DynaModel(TM) for Verilog
model generation of structured-custom designs. Models produced by the
Circuit Semantics tools are used in synthesis, timing-driven
place-and-route, static-timing analysis, noise analysis, power
analysis and functional verification. Tools are targeted for high
performance ASICs, DSP, microprocessor and high-speed communications
ICs.
About Circuit Semantics
Circuit Semantics, Inc. provides electronic design automation
(EDA) software that supports precise, gate-level abstraction and
analysis of transistor-level circuits, and accelerates timing closure
for designs fabricated in nanometer process technologies.
Circuit Semantics is headquartered at 2410 Charleston Road,
Mountain View, CA 94043, telephone 650-564-9100; fax 650-564-9694. For
more information, visit www.circuitsemantics.com.
Acronyms and definitions
ALF The Advanced Library Format or IEEE 1603 standard
is a standard for the language and semantic
representation for design libraries. It supports an
RTL to GDSII descriptions of functional, electrical
performance and layout views for technology libraries,
scalable from cells to complex hierarchical design
blocks.
IEEE Institute of Electrical and Electronic Engineers
SPDM The Scalable Polynomial Delay Model is a Synopsys
delay model used in the Liberty library.
DynaCell, DynaCore and DynaModel are trademarks of Circuit
Semantics, Inc.
All other trademarks are the property of their respective owners.
Contact:
ValleyPR
Georgia Marszalek, 650-345-7477
Georgia@ValleyPR.com
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